module ram(
           input clk,
           input rst,
           input [3: 0] wen,
           input [31: 0] w_addr_i,
           input [31: 0] w_data_i,
           input ren,
           input [31: 0] r_addr_i,

           output [31: 0] r_data_o
       );

wire [11: 0] w_addr = w_addr_i[13: 2];
wire [11: 0] r_addr = r_addr_i[13: 2];

//字节0
dual_ram#(
            .DW ( 8 ),
            .AW ( 12 ),
            .MEM_NUM ( 4096 )
        )u_dual_ram_ram_1(
            .clk ( clk ),
            .rst ( rst ),
            .w_en ( wen[0] ),
            .w_addr_i ( w_addr ),
            .w_data_i ( w_data_i[7: 0] ),
            .r_en ( ren ),
            .r_addr_i ( r_addr ),
            .r_data_o ( r_data_o[7: 0] )
        );

//字节1
dual_ram#(
            .DW ( 8 ),
            .AW ( 12 ),
            .MEM_NUM ( 4096 )
        )u_dual_ram_ram_2(
            .clk ( clk ),
            .rst ( rst ),
            .w_en ( wen[1] ),
            .w_addr_i ( w_addr ),
            .w_data_i ( w_data_i[15: 8] ),
            .r_en ( ren ),
            .r_addr_i ( r_addr ),
            .r_data_o ( r_data_o[15: 8] )
        );


//字节2
dual_ram#(
            .DW ( 8 ),
            .AW ( 12 ),
            .MEM_NUM ( 4096 )
        )u_dual_ram_ram_3(
            .clk ( clk ),
            .rst ( rst ),
            .w_en ( wen[2] ),
            .w_addr_i ( w_addr ),
            .w_data_i ( w_data_i[23: 16] ),
            .r_en ( ren ),
            .r_addr_i ( r_addr ),
            .r_data_o ( r_data_o[23: 16] )
        );

//字节3
dual_ram#(
            .DW ( 8 ),
            .AW ( 12 ),
            .MEM_NUM ( 4096 )
        )u_dual_ram_ram_4(
            .clk ( clk ),
            .rst ( rst ),
            .w_en ( wen[3] ),
            .w_addr_i ( w_addr ),
            .w_data_i ( w_data_i[31: 24] ),
            .r_en ( ren ),
            .r_addr_i ( r_addr ),
            .r_data_o ( r_data_o[31: 24] )
        );


endmodule
